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LANfinityTM RS7112
Multifunction Controller With Integrated HomePNA 1.0 Physical Layer
The introduction of the RS7112 Home Networking multifunction controller with integrated HomePNA 1.0 physical layer presents a simple way to network PCs and peripherals in the home while sharing Internet access. This highly integrated, low-cost, and feature-rich solution combines Conexant's experience with multifunction Ethernet controllers and highspeed analog modems with support for the emerging Home Networking standard. The RS7112 supports the home phoneline networking standard proposed by the Home Phoneline Networking Alliance (HomePNA 1.0). Products that comply with this specification and combine home networking with highspeed Internet access will change the way people use computers at home. The HomePNA phoneline network utilizes existing telephone wiring to connect computers and devices without interrupting phone service. Industry-standard home networking products will enable a variety of home computing opportunities including * * * * shared Internet access using a single phone line printer/peripheral sharing file and application sharing networked gaming
Distinguishing Features
* Single-chip multifunction controller supports both CardBus and PCI Bus interfaces 100 Mbps IEEE 802.3u 100BASE-T compliant 10 Mbps IEEE 802.3 10BASE-T compliant Supports the HomePNA 1 Mbps home phoneline network standard (HomePNA 1.0) Multifunction logic supports simultaneous modem/network operation Power Management Features - PCI Power Management compliant - PCI Power Management for CardBus compliant - PC-98/99 compliant - Network Wake-Up Packet (NWUP) support Supports MAGIC PACKETTM1 WakeUp Technology Supports host-controlled HCF and HSF V.90/K56flexTM modems to reduce system chip count and power requirements Configurable for full-duplex operation on both 10 Mbps and 100 Mbps Separate receive and transmit FIFOs and corresponding DMA controllers Smart TX-DMA/RX-DMA arbitration scheme on full duplex model Supports a variety of flexible address filtering modes Automatic loading of subvendor ID and CardBus Card Information Structure (CIS) pointer from serial ROM to configuration registers -
* * * * *
*
Conexant's success in a variety of core technologies used in the RS7112 allows us to provide a complete home networking solution. In addition to supporting the 1 Mbps home phoneline network standard, the RS7112 supports PCI and CardBus interfaces, 10/100 Ethernet PHYs, and Conexant's line of 56 Kbps (V.90) modems, including both host-controlled (HCF) and soft (HSF) implementations. The RS7112 also incorporates all IEEE 802.3 Media Access Control (MAC) functions, provides complete buffer management, the Media Independent Interface (MII), the 7-wire serial interface, and a Flash ROM interface. When combined with a Conexant HCF or HSF V.90/K56flex modem along with a 10/100 Mbps PHY, the RS7112 can be used to provide a variety of low-cost home networking plus 56 Kbps modem plus 10/100 Mbps LAN solutions.
* * * * *
1 Magic Packet is a trademark of Advanced Micro Devices, Inc.
Data Sheet
Conexant Proprietary Information
Dissemination or use of this information is not permitted without the written permission of Conexant Systems, Inc.
Order No. LAN-047 Rev. D, May 7, 1999
Distinguishing Features (continued)
* * * * * * * * * * * 512 byte CIS RAM for CardBus configuration storage Programmable auto-transmit-padding function Auto-retransmit SNMP 802.3 MIB statistics collection Media Independent Interface (MII) 7-wire serial interface for home phoneline networking support and Ethernet ENDEC components Six general purpose I/O (GPIO) pins and control register General purpose timer 33 MHz operation (using PCI Clock) 3.3 Volt operation with 5 Volt Tolerant I/O 176-pin TQFP package or 13 mm (176-pin) BGA
Ordering Information
Product RS7112 Multifunction PCI/CardBus Ethernet and HomeLAN Controller with Integrated HomePNA 1.0 Physical Layer and 56 Kbps HCF/HSF Modem Interface RS7112-LAN Multifunction PCI/CardBus Ethernet and HomeLAN Controller with Integrated HomePNA 1.0 Physical Layer Only Related Products RS7111A Multifunction PCI/CardBus Ethernet and HomeLAN Controller with V.90 HCF Modem Interface RS7111A-LAN Multifunction PCI/CardBus Ethernet and HomeLAN Controller Only RS7220 HomePNA 1.0 Physical Layer device CN7221 HomePNA 1.0 Physical Layer with Integrated Analog Front End 32-pin TQFP 11625-11 64-pin TQFP R8293-11 176-pin TQFP 11617-12 176-pin TQFP 11617-14 Package 176-pin TQFP 13 mm BGA 176-pin TQFP Device Number 11623-14 11623D11-16 11623-12
Information provided by Conexant Systems, Inc. is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without notice. Conexant, "What's Next in Communications Technologies," and LANfinity are registered trademarks of Conexant Systems, Inc. SoftK56 is a trademark of Conexant Systems, Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. (c)1999, Conexant Systems, Inc. All Rights Reserved
Multifunction Controller With HomePNA 1.0 Physical Layer
LANfinityTM RS7112
Technical Specifications
Description The typical application shown in Figure 1 displays a multifunction PCI Network Interface Card (NIC). The NIC incorporates the RS7112, a V.90 56 Kbps host-controlled (HCF) modem, and a 10/100 Mbps Ethernet PHY. The system shown provides simultaneous Home Networking/modem functionality, or simultaneous Ethernet LAN/modem functionality.
Home Networking
Both modem designs integrate the functionality of a modem controller fully within the host. This results in a reduced chip count that simplifies system designs, lowers system costs, and reduces power requirements. The RS7112's HCF modem interface links directly to a modem datapump, while support for HSF modems provides an even lower system chip count by eliminating the need for a separate modem datapump.
PCI/CardBus Multifunction Interface
The home phoneline network is an Ethernet-compatible LAN running over the random-tree wiring found in nearly all homes. It does not require any hubs, routers, splitters, filters or terminations. Home phoneline networking PC network interface cards will interface home computers directly to the network via an in-home telephone jack. Home phoneline networking will also work with current Internet access technologies, such as cable modems, V.90 and ADSL.
Host-Controlled Modem Interface
The single-chip RS7112 supports both a direct interface to the PCI Bus or CardBus and a modem interface. The integrated multifunction logic provides the capability for simultaneous modem and network operation. The modem interface is linked to a host-controlled modem. The multifunction logic determines for which function, modem or network, the single interrupt request line, INTA, is intended. Interactions between the PC host and RS7112 occur in two modes; programmed I/O (PIO) and bus master. In PIO mode the PC can read and write to control and status registers within the RS7112 target device, using direct or memory-mapped I/O transactions. This provides the host PC with access to all the control and status registers including the flash ROM and serial EEPROM devices using byte, word, or double word transactions. When operating as bus master the RS7112 performs Direct Memory Access (DMA) transactions automatically, transferring Ethernet data between its internal FIFOs and PC host memory using efficient burst transactions.
The RS7112's integrated multifunction logic provides the capability for simultaneous modem and network operation Additionally, the RS7112 supports both HCF and HSF Conexant modems, providing superior system design flexibility.
RS7112
Ethernet MAC/ V.90 Modem Combination
V.90 DSP (optional)
V.90 CODEC
DAA
RJ-11
7-Wire Serial (7WS) Interface
PCI
Home Networking AFE
HomePNA 1.0 Physical Layer Media Independent Interface 10/100 Ethernet PHY RJ-45
MII
Figure 1. Typical Application
LAN-047, Rev. D
Conexant
PROPRIETARY INFORMATION
3
LANfinityTM RS7112
Multifunction Controller With HomePNA 1.0 Physical Layer
Functional Description
GPIO
Modem Function
CODEC Interface
CODEC
Four Channel DMA Controller
MCU
Buffer Interface Logic
Modem RX 8 Byte Modem TX 8 Byte V TX 8 Byte V RX 8 Byte
8-Bit ISA Like Interface
Configuration and Status Registers (CSR) PCI Configuration Registers
Serial Port A Interface Serial 8-Bit Interface
Data Pump
Power Management
PCI\CardBus
Bus Interface
LAN Function
Buffer Interface Logic Two Channel DMA Controller Transmit FIFO Transmit MAC
MII/7WS
LAN PHY
Receive FIFO Receive MAC
MII/7WS
Configuration and Status Registers (CSR)
PCI Configuration Registers
HomePNA 1.0 PHY
EEPROM
Flash ROM (optional)
GPIO
Figure 2. RS7112 Device Architecture Diagram (LAN-only versions do not support modem functionality)
Media Access Controller (MAC) The RS7112 supports the MAC sublayer of the IEEE 802.3. It can operate in half-duplex, full duplex, and loopback modes. In half-duplex mode, the RS7112 checks the line condition before starting to transmit. If the condition is clear, the RS7112 starts transmitting. Full duplex operation allows simultaneous transmission and reception of data that can effectively double data throughput to 20 or 200 Mbps.
Physical Layer (PHY) Interface
Buffer Management
The RS7112 provides a buffer management scheme supporting either chain or ring buffer structures for flexible buffer management. Two DMA engines shuttle the receive and transmit data between the host and RS7112 automatically. The buffer management architecture minimizes data handling of the information, thereby reducing CPU overhead. The packet can be in a single fragment or broken into multiple fragments, and is referenced by either single or multiple descriptors respectively. This allows quick access and minimal handling of the data. Data is transferred in the most efficient manner using PCI burst transfers and direct memory access. Two large independent internal FIFOs, each 32-bits wide, provide multiple data packet transmit and receive buffering with programmable thresholds and store-and-forward modes. The receive FIFO is 4K bytes and the transmit FIFO is 2K bytes.
LAN-047, Rev. D
The integrated HomePNA 1.0 physical layer-portion of the RS7112 resides between the MAC-portion and the physical medium. It is responsible for receiving and transmitting data on the physical medium, detecting collisions on the physical medium, and translating data to and from the MAC-portion of the RS7112.
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Conexant
PROPRIETARY INFORMATION
Multifunction Controller With HomePNA 1.0 Physical Layer
Address Filtering 3.3Vaux Auxiliary Power-On Support
LANfinityTM RS7112
The RS7112 device supports five types of address filtering. Each is described in more detail in the following sections. The filtering is configured through setup frames sent to the RS7112. 16-address perfect filtering: The RS7112 provides support for the perfect filtering of up to 16 Ethernet unicast or multicast addresses. Any mix of addresses can be used. One unicast address perfect and unlimited multicast address imperfect filtering: The RS7112 supports one, single unicast address to be perfectly filtered with an unlimited number of multicast addresses to be imperfectly filtered. Unlimited unicast addresses and multicast addresses imperfect filtering: The RS7112 supports imperfect filtering for an unlimited number of unicast addresses as well as multicast addresses. This feature permits the reception of more than 16 multicast addresses while supporting applications requiring more than one unicast address to be filtered as the station address. Promiscuous mode: The RS7112 supports the reception of all good frames. Pass all multicast: The RS7112 supports the reception of all multicast frames. Loopback Operations The RS7112 supports internal and external loopback modes. Internal loopback mode can be used to verify the correct operation of internal logic operations. External loopback mode can be used to verify that the logic operations up to the Ethernet wire function correctly. Power Management Features
PC-98/99-compliance
The RS7112 supports PC systems that comply with the PCI Bus Power Management Interface Specification. To support keep-alive circuitry, power managed systems must provide an optional 3.3Vaux auxiliary power source because the VCC pins on the PCI expansion slot have been turned off. Auxiliary power can be provided by an on-board battery, an AC adapter (externally provided power source), or by auxiliary power supplied by the system.
Wake-up Technologies Network Wake-Up Packet (NWUP) Support
The RS7112 supports a network wake-up frame detection scheme. Every incoming packet can be checked against a matching wake-up frame template to determine if a wakeup event has occurred. The template is stored in the RS7112's 2 Kbyte transmit FIFO. If a wake-up event has occurred, the RS7112 will restore the host system to a state that will permit the operating system to function. This Wake-on-LAN feature can be used to wake-up a device on the network for a variety of purposes: * * To request network management information To use a service or resource located on the device
MAGIC PACKET
The RS7112 implements power management features to minimize system power consumption, manage system thermal limits, and maximize system battery life. The device complies with the Communications and Network Class Power Management Specifications, PCI Bus Power Management Interface Specification v1.1, and the draft PCI Power Management for CardBus Specification. This assures the device will comply with Microsoft's OnNow and PC-98/99 specifications.
MAGIC PACKET technology has been implemented in the RS7112. A MAGIC PACKET is a protocol independent Ethernet frame sent to a single network node that allows sleeping Green PCs to be remotely woken up. When a MAGIC PACKET is received, the RS7112 device asserts a Power Management Enable (PME) interrupt to wake up the host. Previously, once a Green PC was shutdown to conserve power, network administrators wishing to perform a task had to physically locate the node and turn it on. With MAGIC PACKET technology this function can be performed using software commands from a management console.
Wake on Ring
The RS7112 device supports Wake on Ring, a feature that allows a PC to power on when receiving an incoming call. Upon the first ring received, the device asserts a Power Management Enable (PME) interrupt to wake up the host. It also stores the Caller ID information received between rings. The host powers up upon receiving the interrupt and begins processing the call.
LAN-047, Rev. D
Conexant
PROPRIETARY INFORMATION
5
LANfinityTM RS7112
Multifunction Controller With HomePNA 1.0 Physical Layer
Configuration The serial EEPROM interface is used to load the CIS information required for CardBus information. The CIS information is read from the serial EEPROM and stored in host memory. The RS7112 configuration information requires 21 bytes of data for the modem function and 10 bytes of data for the LAN function. The minimum serial EEPROM size is 512 bytes (4096 bits). The RS7112 device functions as memory slave and bus master for PC memory accesses. One memory block of 64K is allocated to the modem function and one block of 16K is allocated to the LAN function. 7-Wire Serial Interface (7WS) The serial port consists of seven signals that provide a conventional interface to 10 Mbps Ethernet ENDEC components. In addition, the 7WS supports the 1 Mbps home networking PHY. The 7WS signals are multiplexed with the MII signals so that the RS7112 alternately supports either an Ethernet 10/100 PHY or the 1 Mbps home networking PHY. MII Interface The MII port provides a simple and easily implemented interconnection between the RS7112 and PHY sublayer. The MII port is media independent, multi-vendor interoperable, and supports all data rates and physical standards. It consists of data paths that are 4-bits wide in each direction as well as control and management signals.
External Ports
Flash ROM Interface The RS7112 provides a ROM interface that may be optionally used on a network adapter. The flash ROM may contain code that can be executed for device-specific initialization and potentially for system boot. During machine boot, the BIOS looks for bootable devices by searching a specific signature (55AAh). When found, the BIOS copies the code from the Flash ROM to a shadow RAM in the host memory and executes the code from that RAM. The interface supports: * * 3V, 5V, or 12V flash memory Up to 64 KB address space
Serial EEPROM Interface The serial EEPROM interface is used to load the PCI/CardBus configuration information as well as the CIS information required for CardBus information. The CIS information for each function, LAN and modem, is read from the serial EEPROM and stored in each function's internal CIS RAM. The RS7112 PCI/CardBus configuration information requires 25 bytes of data for the modem function and 27 bytes of data for the LAN function. The minimum serial EEPROM size is 512 bytes (4096 bits). The RS7112 device functions as memory slave and bus master for PC memory accesses. One memory block of 64K is allocated to the modem function and one block of 16K is allocated to the LAN function. The CIS information for each function is read from the serial EEPROM and stored in the internal RAM of the RS7112. The serial EEPROM may be programmed in system. The pins of the serial EEPROM are directly programmable via PIO. GPIO Interface The RS7112 provides six General Purpose Input/Output (GPIO) pins. General Purpose pins can be used by software as either status pins or control pins and configured by software to perform either input or output functions. Two GPIO pins are dedicated to modem functionality and the remaining four are dedicated to LAN functionality.
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Conexant
PROPRIETARY INFORMATION
LAN-047, Rev. D
Multifunction Controller With HomePNA 1.0 Physical Layer
LANfinityTM RS7112
Pinout Diagrams2
VDD MDP_SR 8CLK MDP_SR 8FRM SCANMODE MDM_GPIO[0 ] MDM_GPIO[1 ] MDM_GPOL[0] MDP_MTX D MDP_MTX CLK GND MDP_MRXCL K VDD MDM_DRD# MDM_DW R# MDM_CS# MDM_ADDR[4] GND MDM_ADDR[3] MDM_ADDR[2] PCI_VAUXDET CDC_MAS TER_CLK PCI_VAUXEN# MDM_GPI[0] MDM_GPI[1] MDM_GPI[2] MDM_GPI[4] MDM_GPIO[1 5] CDC_M_ STROBE CDC_V _RXOUT GND VDD HLAN_ PEAK HLAN_ SLICE_LVL _PEAK HLAN_ DATA VGG HLAN_ SLICE_LVL _DATA HLAN_ NOIS E HLAN_ SLICE_LVL _NOISE VDD HLAN_ TXP HLAN_ TXPH HLAN_ TXN HLAN_ TXNH GND 13 3 13 4 13 5 13 6 13 7 13 8 13 9 14 0 14 1 14 2 14 3 14 4 14 5 14 6 14 7 14 8 14 9 15 0 15 1 15 2 15 3 15 4 15 5 15 6 15 7 15 8 15 9 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 17 0 17 1 17 2 17 3 17 4 17 5 17 6 13 2 13 1 13 0 12 9 12 8 12 7 12 6 12 5 12 4 12 3 12 2 12 1 12 0 119 118 117 116 115 114 113 112 111 110 10 9 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 10 0 99 98 97 96 95 94 93 92 91 90 89 GND MDP_SR 8RXD MDP_SR 8TXD MDP_MRXD MDP_AD DR[1] MDP_AD DR[0] MDP_DATA[7] PCI_VPCIEN# MDP_DATA[6] MDP_DATA[5] VDD MDM_OSC_ OU T PCI_VPCIDET MDP_DATA[4] MDP_DATA[3] MDP_DATA[2] MDP_DATA[1] GND MDP_DATA[0] MDM_IRQ FROM_CS MDM_SDXTAL 2 MDM_SDXTAL 1 EEPROM _ CS GND VDD EEPROM _ CLK EEPROM _ DIN EEPROM _ DOUT GND HLAN_ OSC GND CARDBUS N# CB_CL KRUN# VDD PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] GND VDD PCI_AD[5] PCI_AD[6]
VDD LAN_ GPIO[0] 80 23_MII_CRS 80 23_MII_COL 80 23_MII_TXD[3] 80 23_MII_TXD[2] SCANEN B 80 23_MII_TXD[1] 80 23_MII_TXD[0] 80 23_MII_TX_E N 80 23_MII_TX_CL K VDD 80 23_MII_TX_E R 80 23_MII_RX_ER 80 23_MII_RX_CL K GND 80 23_MII_RX_DV 80 23_MII_RXD[0] 80 23_MII_RXD[1] VDD 80 23_MII_RXD[2] 80 23_MII_RXD[3] GND 80 23_MII_MDC 80 23_MII_MDIO PCI_PME PCI_INT# PCI_RST# VDD PCI_CLK GND PCI_GNT# PCI_REQ# PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] VDD GND PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_C/BE#[3]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
PIN 1 REF
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
74)3
Figure 3. RS7112 176-pin TQFP Pinout Diagram (Device Number 11623-14)
2 Logic low active signals are followed by a pound (#).
LAN-047, Rev. D
VDD GND PCI_IDSEL PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] VDD GND PCI_AD[19] PCI_AD[18] VGG PCI_AD[17] PCI_AD[16] PCI_C/BE#[2] VDD GND PCI_FRAME# PCI_IRDY# PCI_TRDY# VDD GND PCI_DEVSE L# PCI_STOP# PCI_PERR# VDD GND PCI_SERR# PCI_PAR PCI_C/BE#[1] PCI_AD[15] PCI_AD[14] VDD GND PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] VDD GND PCI_AD[8] PCI_C/BE#[0] PCI_AD[7]
Conexant
PROPRIETARY INFORMATION
7
LANfinityTM RS7112
Multifunction Controller With HomePNA 1.0 Physical Layer
A1 BALL PAD CORNER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0.80
A B C D E F G H J K
0.90 REF
L M N P R
0.90 REF
0.80
BOTTOM VIEW
(176 SOLDER BALLS)
Refer also to Table 2, 176-pin BGA Pin Designations by Number.
Figure 4. RS7112 176-pin BGA Pinout Diagram (Device Number 11623D11-16)
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Conexant
PROPRIETARY INFORMATION
LAN-047, Rev. D
Multifunction Controller With HomePNA 1.0 Physical Layer
LANfinityTM RS7112
VDD NC NC SCANMODE NC NC NC NC GND GND GND VDD NC NC NC NC GND NC NC PCI_VAUXDET NC PCI_VAUXEN# GND GND GND GND NC GND GND GND VDD HLAN_ PEAK HLAN_ SLICE_LVL _PEAK HLAN_ DATA VGG HLAN_ SLICE_LVL _DATA HLAN_ NOIS E HLAN_ SLICE_LVL _NOISE VDD HLAN_ TXP HLAN_ TXPH HLAN_ TXN HLAN_ TXNH GND 13 3 13 4 13 5 13 6 13 7 13 8 13 9 14 0 14 1 14 2 14 3 14 4 14 5 14 6 14 7 14 8 14 9 15 0 15 1 15 2 15 3 15 4 15 5 15 6 15 7 15 8 15 9 16 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 17 0 17 1 17 2 17 3 17 4 17 5 17 6 13 2 13 1 13 0 12 9 12 8 12 7 12 6 12 5 12 4 12 3 12 2 12 1 12 0 119 118 117 116 115 114 113 112 111 110 10 9 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 1 10 0 99 98 97 96 95 94 93 92 91 90 89 GND NC GND GND NC NC NC PCI_VPCIEN# NC NC VDD NC PCI_VPCIDET NC NC NC NC GND NC GND FROM_CS NC GND EEPROM _ CS GND VDD EEPROM _ CLK EEPROM _ DIN EEPROM _ DOUT GND HLAN_ OSC GND CARDBUS N# CB_CL KRUN# VDD PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] GND VDD PCI_AD[5] PCI_AD[6]
VDD LAN_ GPIO[0] 80 23_MII_CRS 80 23_MII_COL 80 23_MII_TXD[3] 80 23_MII_TXD[2] SCANEN B 80 23_MII_TXD[1] 80 23_MII_TXD[0] 80 23_MII_TX_E N 80 23_MII_TX_CL K VDD 80 23_MII_TX_E R 80 23_MII_RX_ER 80 23_MII_RX_CL K GND 80 23_MII_RX_DV 80 23_MII_RXD[0] 80 23_MII_RXD[1] VDD 80 23_MII_RXD[2] 80 23_MII_RXD[3] GND 80 23_MII_MDC 80 23_MII_MDIO PCI_PME PCI_INT# PCI_RST# VDD PCI_CLK GND PCI_GNT# PCI_REQ# PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] VDD GND PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_C/BE#[3]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
PIN 1 REF
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
74)3
Figure 5. RS7112-LAN 176-pin TQFP Pinout Diagram (Device Number 11623-12)
LAN-047, Rev. D
VDD GND PCI_IDSEL PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] VDD GND PCI_AD[19] PCI_AD[18] VGG PCI_AD[17] PCI_AD[16] PCI_C/BE#[2] VDD GND PCI_FRAME# PCI_IRDY# PCI_TRDY# VDD GND PCI_DEVSE L# PCI_STOP# PCI_PERR# VDD GND PCI_SERR# PCI_PAR PCI_C/BE#[1] PCI_AD[15] PCI_AD[14] VDD GND PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] VDD GND PCI_AD[8] PCI_C/BE#[0] PCI_AD[7]
Conexant
PROPRIETARY INFORMATION
9
LANfinityTM RS7112
Multifunction Controller With HomePNA 1.0 Physical Layer
Table 1. RS7112 176-pin TQFP Pin Designations by Number3 (Device Number 11623-14)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Signal VDD LAN_GPIO[0] 8023_MII_CRS 8023_MII_COL 8023_MII_TXD[3] 8023_MII_TXD[2] SCANENB 8023_MII_TXD[1] 8023_MII_TXD[0] 8023_MII_TX_EN 8023_MII_TX_CLK VDD 8023_MII_TX_ER 8023_MII_RX_ER 8023_MII_RX_CLK GND 8023_MII_RX_DV 8023_MII_RXD[0] 8023_MII_RXD[1] VDD 8023_MII_RXD[2] 8023_MII_RXD[3] GND 8023_MII_MDC 8023_MII_MDIO PCI_PME PCI_INT# PCI_RST# VDD PCI_CLK GND PCI_GNT# PCI_REQ# PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] VDD GND PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_C/BE#[3]
Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Signal VDD GND PCI_IDSEL PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] VDD GND PCI_AD[19] PCI_AD[18] VGG PCI_AD[17] PCI_AD[16] PCI_C/BE#[2] VDD GND PCI_FRAME# PCI_IRDY# PCI_TRDY# VDD GND PCI_DEVSEL# PCI_STOP# PCI_PERR# VDD GND PCI_SERR# PCI_PAR PCI_C/BE#[1] PCI_AD[15] PCI_AD[14] VDD GND PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] VDD GND PCI_AD[8] PCI_C/BE#[0] PCI_AD[7]
Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
Signal PCI_AD[6] PCI_AD[5] VDD GND PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_AD[0] VDD CB_CLKRUN# CARDBUSN# GND HLAN_OSC GND EEPROM_DOUT EEPROM_DIN EEPROM_CLK VDD GND EEPROM_CS MDM_SDXTAL1 MDM_SDXTAL2 FROM_CS MDM_IRQ MDP_DATA[0] GND MDP_DATA[1] MDP_DATA[2] MDP_DATA[3] MDP_DATA[4] PCI_VPCIDET MDM_OSC_OUT VDD MDP_DATA[5] MDP_DATA[6] PCI_VPCIEN# MDP_DATA[7] MDP_ADDR[0] MDP_ADDR[1] MDP_MRXD MDP_SR8TXD MDP_SR8RXD GND
Pin No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
Signal VDD MDP_SR8CLK MDP_SR8FRM SCANMODE MDM_GPIO[0] MDM_GPIO[1] MDM_GPOL[0] MDP_MTXD MDP_MTXCLK GND MDP_MRXCLK VDD MDM_DRD# MDM_DWR# MDM_CS# MDM_ADDR[4] GND MDM_ADDR[3] MDM_ADDR[2] PCI_VAUXDET CDC_MASTER_CLK PCI_VAUXEN# MDM_GPI[0] MDM_GPI[1] MDM_GPI[2] MDM_GPI[4] MDM_GPIO[15] CDC_M_STROBE CDC_V_RXOUT GND VDD HLAN_PEAK HLAN_SLICE_LVL_PEAK HLAN_DATA VGG HLAN_SLICE_LVL_DATA HLAN_NOISE HLAN_SLICE_LVL_NOISE VDD HLAN_TXP HLAN_TXPH HLAN_TXN HLAN_TXNH GND
3 Logic low active signals are followed by a pound (#). Multiplexed signals are in italics.
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Conexant
PROPRIETARY INFORMATION
LAN-047, Rev. D
Multifunction Controller With HomePNA 1.0 Physical Layer
Table 2. RS7112 176-pin BGA Pin Designations by Number4 (Device Number 11623D11-16)
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Signal VDD GND HLAN_TXN HLAN_TXPH VDD HLAN_SLICE_LVL_DATA VDD MDM_GPIO[15] MDM_ADDR[3] MDM_DWR# MDP_MTXCLK MDM_GPIO[1] SCANMODE MDP_SR8FRM VDD 8023_MII_CRS LAN_GPIO[0] HLAN_TXNH HLAN_TXP VGG HLAN_PEAK CDC_M_STROBE MDM_GPI[1] CDC_MASTER_CLK GND MDM_DRD# GND MDM_GPIO[0] MDP_SR8CLK GND 8023_MII_COL 8023_MII_TXD[3] HLAN_SLICE_LVL_NOISE HLAN_DATA GND MDM_GPI[4] MDM_GPI[0] PCI_VAUXEN# MDM_ADDR[2] MDM_CS# MDP_MRXCLK MDM_GPOL[0] MDP_DATA[7] MDP_SR8RXD Pin No. C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E12 E13 E14 E15 F1 F2 F3 F4 F12 F13 F14 F15 G1 G2 G3 G4 G12 G13 G14 G15 H1 H2 H3 H4 Signal MDP_SR8TXD 8023_MII_TXD[2] 8023_MII_TX_EN SCANENB HLAN_NOISE HLAN_SLICE_LVL_PEAK CDC_V_RXOUT MDM_GPI[2] PCI_VAUXDET MDM_ADDR[4] VDD MDP_MTXD PCI_VPCIEN# VDD MDP_ADDR[1] MDP_MRXD 8023_MII_TXD[0] 8023_MII_TX_ER 8023_MII_TX_CLK 8023_MII_TXD[1] MDM_OSC_OUT MDP_DATA[3] MDP_DATA[5] MDP_ADDR[0] 8023_MII_RX_ER 8023_MII_RX_DV 8023_MII_RX_CLK VDD MDP_DATA[2] MDP_DATA[0] PCI_VPCIDET MDP_DATA[6] 8023_MII_RXD[0] 8023_MII_RXD[2] 8023_MII_RXD[1] GND MDM_IRQ MDM_SDXTAL2 MDP_DATA[1] MDP_DATA[4] PCI_INT# 8023_MII_MDC 8023_MII_RXD[3] VDD Pin No. H12 H13 H14 H15 J1 J2 J3 J4 J12 J13 J14 J15 K1 K2 K3 K4 K12 K13 K14 K15 L1 L2 L3 L4 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 N1 Signal GND MDM_SDXTAL1 FROM_CS GND GND PCI_RST# GND 8023_MII_MDIO EEPROM_DOUT VDD EEPROM_CS EEPROM_CLK PCI_AD[29] PCI_GNT# PCI_PME VDD CARDBUSN# GND EEPROM_DIN HLAN_OSC GND PCI_AD[30] PCI_CLK PCI_REQ# PCI_AD[1] CB_CLKRUN# GND PCI_AD[0] PCI_AD[26] PCI_AD[27] PCI_AD[31] PCI_AD[28] VDD VGG VDD PCI_TRDY# PCI_PERR# PCI_PAR VDD PCI_AD[11] PCI_AD[2] VDD PCI_AD[3] PCI_AD[25] Pin No. N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Signal
LANfinityTM RS7112
PCI_AD[24] VDD PCI_AD[20] PCI_AD[18] PCI_C/BE#[2] PCI_IRDY# GND PCI_DEVSEL# VDD PCI_C/BE#[1] GND PCI_AD[10] PCI_AD[4] GND PCI_C/BE#[3] GND PCI_AD[22] PCI_AD[19] PCI_AD[17] GND VDD PCI_STOP# PCI_SERR# PCI_AD[14] PCI_AD[13] VDD PCI_C/BE#[0] PCI_AD[5] VDD VDD PCI_IDSEL PCI_AD[23] PCI_AD[21] GND PCI_AD[16] PCI_FRAME# GND PCI_AD[15] PCI_AD[12] PCI_AD[9] GND PCI_AD[8] PCI_AD[7] PCI_AD[6]
Refer to Figure 4 for position of pins on BGA
4 Logic low active signals are followed by a pound (#). Multiplexed signals are in italics.
LAN-047, Rev. D
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PROPRIETARY INFORMATION
11
LANfinityTM RS7112
Multifunction Controller With HomePNA 1.0 Physical Layer
Table 3. RS7112-LAN 176-pin TQFP Pin Designations by Number5 (Device Number 11623-12)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Signal VDD LAN_GPIO[0] 8023_MII_CRS 8023_MII_COL 8023_MII_TXD[3] 8023_MII_TXD[2] SCANENB 8023_MII_TXD[1] 8023_MII_TXD[0] 8023_MII_TX_EN 8023_MII_TX_CLK VDD 8023_MII_TX_ER 8023_MII_RX_ER 8023_MII_RX_CLK GND 8023_MII_RX_DV 8023_MII_RXD[0] 8023_MII_RXD[1] VDD 8023_MII_RXD[2] 8023_MII_RXD[3] GND 8023_MII_MDC 8023_MII_MDIO PCI_PME PCI_INT# PCI_RST# VDD PCI_CLK GND PCI_GNT# PCI_REQ# PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] VDD GND PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] PCI_C/BE#[3] Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Signal VDD GND PCI_IDSEL PCI_AD[23] PCI_AD[22] PCI_AD[21] PCI_AD[20] VDD GND PCI_AD[19] PCI_AD[18] VGG PCI_AD[17] PCI_AD[16] PCI_C/BE#[2] VDD GND PCI_FRAME# PCI_IRDY# PCI_TRDY# VDD GND PCI_DEVSEL# PCI_STOP# PCI_PERR# VDD GND PCI_SERR# PCI_PAR PCI_C/BE#[1] PCI_AD[15] PCI_AD[14] VDD GND PCI_AD[13] PCI_AD[12] PCI_AD[11] PCI_AD[10] PCI_AD[9] VDD GND PCI_AD[8] PCI_C/BE#[0] PCI_AD[7] Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Signal PCI_AD[6] PCI_AD[5] VDD GND PCI_AD[4] PCI_AD[3] PCI_AD[2] PCI_AD[1] PCI_AD[0] VDD CB_CLKRUN# CARDBUSN# GND HLAN_OSC GND EEPROM_DOUT EEPROM_DIN EEPROM_CLK VDD GND EEPROM_CS GND NC FROM_CS GND NC GND NC NC NC NC PCI_VPCIDET NC VDD NC NC PCI_VPCIEN# NC NC NC GND GND NC GND Pin No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Signal VDD NC NC SCANMODE NC NC NC NC GND GND GND VDD NC NC NC NC GND NC NC PCI_VAUXDET NC PCI_VAUXEN# GND GND GND GND NC GND GND GND VDD HLAN_PEAK HLAN_SLICE_LVL_PEAK HLAN_DATA VGG HLAN_SLICE_LVL_DATA HLAN_NOISE HLAN_SLICE_LVL_NOISE VDD HLAN_TXP HLAN_TXPH HLAN_TXN HLAN_TXNH GND
5 Logic low active signals are followed by a pound (#).
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PROPRIETARY INFORMATION
LAN-047, Rev. D
Multifunction Controller With HomePNA 1.0 Physical Layer
Table 4. Pin Designations by Group6 PCI/CardBus Signals7
Pin Name PCI_AD[31:0] PCI_C/BE#[3:0] Type I/O I/O Schmitt Resistive Drive
PCI CardBus PCI CardBus
LANfinityTM RS7112
Description Multiplexed Address/Data Command/Byte Enables for PCI/CardBus Bus Indicates the bytes to be transferred in the currently addressed DWORD as well as the data path(s) to be used during the transfer.
& & & & & & & & &
PCI_FRAME#
I/O
PCI CardBus
Frame Driven by the transaction initiator to indicate the start and duration of the transaction.
PCI_IRDY#
I/O
PCI CardBus
Initiator Ready Driven by the current Bus Master. Indicates that the Bus Master is driving valid data on the bus or is ready to accept valid data.
PCI_TRDY#
I/O
PCI CardBus
Target Ready Driven by the current Target to indicate that it is ready to complete the current data phase.
PCI_PAR
I/O
PCI CardBus
Parity (Even) Driven by the initiator or the target to ensure even parity of the AD and C/BE# lines.
PCI_STOP# PCI_DEVSEL# PCI_IDSEL
I/O I/O I

PCI CardBus PCI CardBus
Target Stop Asserted by the Target to stop the current transaction. Device Select Asserted by the Target when the Target has decoded its address. Initialization Device Select An input to a PCI device used as a chip select during access to a device's configuration register(s). This signal should be tied high (asserted) in a CardBus environment
PCI_PERR# PCI_SERR# PCI_REQ# PCI_GNT#
I/O I/O O I
&

PCI CardBus PCI CardBus PCI CardBus
Parity Error Asserted by the Target to indicate that a parity error was detected. System Error Used by a PCI device to indicate a catastrophic system error. Master Request Asserted by a Bus Master to request access to the bus. Grant Asserted by the Bus Master Arbiter to indicate that it is the particular Master's turn to use the bus.
& & & &

PCI_CLK
I
PCI Clock Signal Input to all devices residing on the PCI bus. All inputs are sampled on the rising edge of the PCI_CLK signal.
PCI_RST# PCI_INT# PCI_PME
I O O

PCI CardBus
Reset Causes all PCI devices to return to an initialized state. Interrupt Asserted by a PCI device to indicate a hardware interrupt. PCI/CardBus Power Management Event Signal.
2mA
6 Logic low active signals are followed by a pound (#). Open drain signals are designated by OD. Tristate signals are
indicated by TS and Sustained Tri State signals by STS. Sustained tristate signals are driven high before going into tri-state. = does not apply, & = does not support, ' = supports Schmitt: Resistive: = does not apply, = pull-up, = pull-down 7 See PCI Local Bus Specification, Rev. 2.1, April 1994
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PROPRIETARY INFORMATION
13
LANfinityTM RS7112
Pin Name Type Schmitt Resistive Drive
Multifunction Controller With HomePNA 1.0 Physical Layer
Description This signal is active high and requires an external FET to connect to PCI PME#.
CB_CLKRUN#
I/O
& &
CardBus
Clock Run signal for CardBus This signal should be tied low (always asserted) in a PCI environment since the PCI Bus does not provide this signal.
CARDBUSN#
I
Controls the drive strength of bus interface signals. 0: CardBus 1: PCI
Home LAN
Pin Name HLAN_OSC HLAN_TXP HLAN_TXPH HLAN_TXNH HLAN_TXN HLAN_SLICE_LVL_NOISE HLAN_SLICE_LVL_DATA HLAN_SLICE_LVL_PEAK HLAN_NOISE HLAN_PEAK HLAN_DATA Type I O O O O O O O I I I Schmitt Resistive Drive CMOS 12mA 12mA 12mA 12mA 6mA 6mA 6mA CMOS CMOS CMOS Description 60 MHz oscillator input Positive transmit output High-power positive transmit output High-power negative transmit output High power negative transmit output Pulse width modulated D/A output for slice level on NOISE comparator Pulse width modulated D/A output for slice level on DATA comparator Pulse width modulated D/A output for slice level on PEAK comparator Rising edge on signal crossing NOISE threshold Rising edge on signal crossing PEAK threshold Rising edge on signal crossing DATA threshold
Codec Interface
Pin Name CDC_M_STROBE CDC_V_RXOUT CDC_V_CTRL Type Schmitt Resistive Drive Description Serial Frame Synchronization (strobe) Serial data input from Voice Serial Control Output
multiplexed signal MDM_DRD#
CDC_M_RXOUT Serial Data from Codec
multiplexed signal MDP_MRXD
CDC_MASTER_C LK CDC_M_CTRL Codec Master Clock Serial Control Output
multiplexed signal MDP_SR8TXD
CDC_V_STROBE Serial Frame Synchronization (strobe)
multiplexed signal MDP_SR8RXD
CDC_M_TXSIN Serial Data to Codec
multiplexed signal MDP_MTXD
CDC_V_CLK Voice Clock from Modem Codec
multiplexed signal
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PROPRIETARY INFORMATION
LAN-047, Rev. D
Multifunction Controller With HomePNA 1.0 Physical Layer
Pin Name Type Schmitt Resistive Drive Description
LANfinityTM RS7112
MDP_MTXCLK
CDC_V_TXSIN Serial output to Voice Codec
multiplexed signal MDM_DWR#
CDC_M_CLK Modem clock from Modem IA
multiplexed signal MDP_MRXCLK
Serial Peripheral Interface (SPI) Signals
Pin Name SPI_DOUT Type O Schmitt Resistive Drive 2ma Description Serial Peripheral Interface (SPI) Data Output Data is read from an external SPI device on this pin. See the LANfinity Software Designer's Guide's documentation on the LAN Serial Port Register for information on driving this signal using software. I
multiplexed signal EEPROM_DOUT
SPI_DIN
&
Serial Peripheral Interface (SPI) Data Input Data is written to an SPI device using this pin. See the LANfinity Software Designer's Guide's documentation on the LAN Serial Port Register for information on driving this signal using software.
multiplexed signal EEPROM_DIN
SPI_CLK O 2ma
Serial Peripheral Interface Clock This pin serves as the clock for an external device. Software is responsible for generating the clock. See the LANfinity Software Designer's Guide's documentation on the LAN Serial Port Register for information on driving this signal using software. Refer to the serial device's data sheet to determine the maximum clock rate the device can support.
multiplexed signal EEPROM_CLK
PCI Power Management Signals
Pin Name PCI_VAUXEN# PCI_VPCIEN# Defined for PCI Only PCI_VPCIDET Defined for PCI Only PCI_VAUXDET Defined for PCI Only I I Type O O Schmitt Resistive Drive 2mA 2mA Description 1 = Disable the FET connecting VAUX power supply to the Device 0 = enable the FET. Optional for WAKE UP 1 = enables the Vpci FET
' '
Logical input connected to Vpci
Logic input connected to 3.3Vaux
Modem Data Pump (MDP) Signals
Pin Name MDM_ADDR[4:2] MDM_DWR# Type O O Schmitt Resistive Drive 2ma 2ma Description Address Lines to MCU or MDP Modem Device Write Enable Connected to MCU or MDP O 2ma Modem Device Read Enable Connected to MCU or MDP
multiplexed signal CDC_V_TXSIN
MDM_DRD#
multiplexed signal CDC_V_CTRL
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PROPRIETARY INFORMATION
15
LANfinityTM RS7112
Pin Name MDM_CS# MDM_IRQ MDM_GPI[0] MDM_GPI[1] MDM_GPI[2] MDM_GPI[4] MDM_GPIO[1:0] MDM_GPOL[0] MDP_MRXD Type O I I I I I I/O O I Schmitt Resistive 75Kohm Drive 2ma
Multifunction Controller With HomePNA 1.0 Physical Layer
Description MDP Chip Select MDP Interrupt Request General Purpose Input for Modem Function
& ' '
'

12m A 4mA
General Purpose I/O pins General Purpose Output for Modem Function Reset to low after deassertion of PCI_RST#. Modem Receive Data from Data Pump
& & &
multiplexed signal CDC_M_RXOUT
MDP_MRXCLK I Modem Receive Clock from MDP
multiplexed signal CDC_M_CLK
MDP_MTXCLK I Modem Transmit Clock from MDP
multiplexed signal CDC_V_CLK
MDP_MTXD O 2mA Modem Transmit Data to MDP
multiplexed signal CDC_M_TXSIN
MDP_SR8CLK MDP_SR8TXD I/O O
&

4mA 2mA
Serial interface clock from MDP Serial interface Transmit Data to MDP
multiplexed signal CDC_M_CTRL
MDP_SR8RXD I
& & ' &
Serial interface Receive Data from MDP
multiplexed signal CDC_V_STROBE
MDP_SR8FRM MDM_GPIO[15] MDM_SDXTAL1 MDM_SDXTAL2 MDP_DATA[7:0] MDM_OSC_OUT MDP_ADDR[1:0] O I/O I/O I O 4mA Serial Interface Frame signal from MDP General Purpose Input/Output for Modem Function 28.224 MHz clock for running Modem interface Should be tied to clock output of MDP or an oscillator
LAN Flash ROM Interface Signals
Pin Name FROM_CS# Type O Schmitt Resistive Drive 2ma Description Flash ROM Chip Select
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LAN-047, Rev. D
Multifunction Controller With HomePNA 1.0 Physical Layer
7-Wire Serial Interface Signals
Pin Name 7WS_TX_CLK Type I Schmitt Resistive Drive Description Transmit Clock Transmit Clock from Physical Layer (PHY) to MAC.
LANfinityTM RS7112
&
multiplexed signal 8023_MII_TX_CLK
7WS_TXD O 2ma
Provided as a clock for MAC activity. The rising edges may be used to validate 7WS_TXD. Transmit Data Transmit Data bus from the MAC to the PHY. 7WS_TXD is a bit provided by the MAC synchronously with 7WS_TX_CLK. The bit stream includes preamble, SFD, data and CRC, if enabled. O 2ma Transmit Enable Transmit Enable indicator from MAC to PHY indicates that valid data is being presented on 7WS_TXD. 7WS_TX_EN is synchronized with the 7WS_TX_CLK and is sampled synchronously with 7WS_TX_CLK by the PHY. The 7WS_TX_EN is asserted by the MAC on the first byte of the preamble and remains asserted until the last bit of the frame is transferred. I
multiplexed signal 8023_MII_TXD[3]
7WS_TX_EN
multiplexed signal 8023_MII_TX_EN
7WS_CRS
&
Carrier Sense Provided by the PHY to indicate that Carrier is currently present on the physical media. If this signal is high it indicates that valid data is available on 7WS_RXD or you are transferring in half-duplex mode.
multiplexed signal 8023_MII_CRS
7WS_COL
I
& &
Collision Indication Provided by the PHY to indicate that a collision has been detected on the physical media.
multiplexed signal 8023_MII_COL
7WS_RX_CLK I
Receive Clock A recovered clock provided to the MAC synchronously with 7WS_RXD. If 7WS_RX_DV is high, 7WS_RXD is sampled on the rising edges of this clock.
multiplexed signal 8023_MII_RX_CLK
7WS_RXD I
&
Receive Data Receive Data bus from the PHY to the MAC. 7WS_RXD is accepted by the MAC for each clock period of 7WS_RX_CLK while 7WS_RX_EN is asserted. 7WS_RXD is a bit which is provided by the PHY synchronously with 7WS_RX_CLK. If 7WS_RX_DV is high, 7WS_RXD is sampled on the rising edges of 7WS_RX_CLK.
multiplexed signal 8023_MII_RXD[3]
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PROPRIETARY INFORMATION
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LANfinityTM RS7112
Media Independent Interface (MII)8
Pin Name 8023_MII_TX_CLK Type I Schmitt Resistive Drive
Multifunction Controller With HomePNA 1.0 Physical Layer
Description Transmit Clock Transmit Clock from Physical Layer (PHY) to MAC This clock is provided by the PHY as a reference for the MAC. At both 10 Mbps and 100 Mbps, the permissible duty cycle is between 40% to 60%. The nominal case is 50% 25 MHz 100 PPM in 100 Mbps mode 2.5 MHz 100 PPM in 10 Mbps mode
&
multiplexed signal 7WS_TX_CLK
8023_MII_TXD[3]
O
2ma
Transmit Data Transmit data bus from the MAC to the PHY. 8023_MII_TXD are provided for transmission for each clock period 0f 8023_MII_TX_CLK while 8023_MII_TX_EN is asserted. 8023_MII_TXD[3:0} is a 4-bit data nibble which is provided by the MAC synchronously to 8023_MII_TX_CLK.
multiplexed signal 7WS_TXD
8023_MII_TXD[2] 8023_MII_TXD[1] 8023_MII_TXD[0] 8023_MII_TX_EN O O O O 2ma 2ma 2ma 2ma
Transmit Enable Transmit Enable indicator from MAC to PHY indicates that valid 4-bit nibble of data is being presented at 8023_MII_TXD[3:0]. 8023_MII_TX_EN is synchronized with the 8023_MII_TX_CLK and is sampled synchronously with 8023_MII_TX_CLK by the PHY. The 8023_MII_TX_EN is asserted by the MAC on the first byte of the preamble and remains asserted until the last nibble/bit of the frame is transferred.
multiplexed signal 7WS_TX_EN
8023_MII_TX_ER
O
2ma
Transmit Error Used by the MAC to indicate to the PHY that a coding or transmit underrun error has occurred. Transmit Error is asserted synchronously to 8023_MII_TX_CLK while 8023_MII_TX_EN is asserted to indicate a Transmit Coding Error or transmit underrun of a frame. It is intended to provide a frame abort mechanism and shall cause the PHY to emit one or more ABORT control symbols. The ABORT control symbol is not a valid symbol for Ethernet, therefore, the receiving MAC will recognize the invalid control symbol and indicate a receive error at the receiving end.
8023_MII_MDC
O
2ma
Management Data Clock Clock for Serial Management Interface (SMI). Software provides 8023_MII_MDC to the PHY as a reference clock. It is used in conjunction with the 8023_MII_MDIO signal for reading or writing Link Management or Operation information to and from the PHY.
8023_MII_MDIO
I/O
&
2ma
Serial Management Data Input/Output I/O signal for SMI. This pin is used to read/write data to/from the PHY. Data is synchronized with 8023_MII_MDC. When connecting the MAC to an MII connector instead of a PHY, an external 1.5k ohm pull-up resistor is recommended for this line to allow the attached MAC to determine the attachment of a PHY.
8023_MII_CRS
I
& &
Carrier Sense Provided by the PHY to indicate that Carrier is currently present on the physical media.
multiplexed signal 7WS_CRS
8023_MII_COL I
Collision indication Provided by the PHY to indicate that a collision has been detected on the physical media.
multiplexed signal
8 See IEEE 802.3u Section 22
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PROPRIETARY INFORMATION
LAN-047, Rev. D
Multifunction Controller With HomePNA 1.0 Physical Layer
Pin Name Type Schmitt Resistive Drive Description
LANfinityTM RS7112
7WS_COL
8023_MII_RX_DV I
&
Receive data valid Provided by the PHY to indicate to the MAC that a valid 4-bit nibble of data is available on 8023_MII_RXD[3:0]. 8023_MII_RX_DV is synchronized with 8023_MII_RX_CLK by the PHY and is sampled synchronously with 8023_MII_RX_CLK by the MAC. 8023_MII_RX_DV is asserted by the PHY on the first nibble of the preamble and remains asserted until the last nibble of the frame, excluding any end of frame delimiter, is transferred from the PHY to the MAC.
8023_MII_RX_ER
I
&
Receive Error Produced by the PHY to indicate that it has detected an error in the current packet. This signal is only valid when 8023_MII_RX_DV is asserted.
8023_MII_RX_CLK
I
&
Receive Clock Produced by PHY as a timing reference for 8023_MII_RX_DV, 8023_MII_RXD, and 8023_MII_RX_ER signals. The permissible duty cycle is between 35% and 65% inclusive. The nominal case is 50%. 25 MHz 2500 Hz in 100 Mbps mode 2.5MHz 250Hz in 10 Mbps mode 8023_MII_RX_CLK and 8023_MII_TX_CLK may be referenced from the same source.
multiplexed signal 7WS_RX_CLK
8023_MII_RXD[3]
I
& & & &
Receive Data Receive Data bus from the PHY to the MAC. 8023_MII_RXD[3:0] are accepted by the MAC for each clock period of 8023_MII_RX_CLK while 8023_MII_RX_EN is asserted. 8023_MII_RXD[3:0] is a 4-bit data nibble which is provided by the PHY synchronously to 8023_MII_RX_CLK.
multiplexed signal 7WS_RXD
8023_MII_RXD[2] 8023_MII_RXD[1] 8023_MII_RXD[0] I I I
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PROPRIETARY INFORMATION
19
LANfinityTM RS7112
IEEE 802.3 Fast Ethernet Signals
Pin Name LAN_GPIO[0] Type I/O Schmitt Resistive Drive 4mA
Multifunction Controller With HomePNA 1.0 Physical Layer
Description LAN Function General Purpose I/O pin May be individually configured for input/output using the LAN_GPIO register. If configured for input it can generate level sensitive hardware interrupts. May be used to reset peripheral devices that require active high reset.
&
Serial EEPROM Interface Signals
Pin Name EEPROM_DOUT Type O Schmitt Resistive Drive 2ma Description EEPROM Data Output Data is read from an external EEPROM on this pin. The pin must have a 10K pull-up or pull-down attached on the board. Pulling the pin low (logical 0) will cause the MAC to skip the EEPROM Read process after a PCI RST# is de-asserted. See the LANfinity Software Designer's Guide's documentation on the LAN Serial Port Register for information on driving this signal using software. I
multiplexed signal SPI_DOUT
EEPROM_DIN
&
EEPROM Data Input Data is written to an EEPROM device using this pin. This pin requires a 51K pull-down on the adapter. See the LANfinity Software Designer's Guide's documentation on the LAN Serial Port Register for information on driving this signal using software.
multiplexed signal SPI_DIN

EEPROM_CS
O
2ma
EEPROM Chip Select This pin acts as the Chip Select for an external EEPROM. Refer to the RS7xxx Software Design Guide documentation on the LAN Serial Port Register for information about driving this signal using software. Note: This pin requires a 51K pull-down on the adapter
EEPROM_CLK
O
2ma
EEPROM Clock This pin serves as the clock for an external EEPROM. Following a reset of the device, the MAC controls the duty cycle during the automatic read process. Software is responsible for generating the clock during any reading or programming of the EEPROM. This pin requires a 51K pulldown on the adapter. See the LANfinity Software Designer's Guide's documentation on the LAN Serial Port Register for information on driving this signal using software. During the automatic read from EEPROM the CMAC will use the clock rate indicated: VCC 5V 3.3V Clock 2 MHz 1 MHz
multiplexed signal SPI_CLK
Refer to the EEPROM device's data sheet to determine the maximum clock rate the device can support.
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PROPRIETARY INFORMATION
LAN-047, Rev. D
Multifunction Controller With HomePNA 1.0 Physical Layer
Test Signals
Pin Name SCANMODE SCANENB Type I I Schmitt Resistive Drive Description Selects different scan modes Scan enable (1 = enable scan)
LANfinityTM RS7112
& &
Power Pins
Pin Name VDD GND VGG Type P G P Characteristic 3V GND 5V Description 3.3 Volt Power Ground 5 V - attach to 5 V clamping during 3.3 V operation
Electrical Characteristics
176-pin TQFP
Table 5. Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Voltage Applied to Outputs in High Z state DC Input Clamp Current DC Input Clamp Current Static Discharge Voltage (25 oC) Latch-up Current Symbol VDD VIN T Tstg Vhz Ilk Iok ESD Itrig 0 -65 -0.5 -20 -20 -2500 -400 Min Typ 3.3 TBD TBD TBD TBD TBD TBD TBD TBD +70 +150 TBD +20 +20 +2500 +400 Max Units V V oC oC V mA mA V mA
Table 6. DC Electrical Characteristics o o TA = 0 C to +70 C, VDD = +3.3V 5%, VSS = 0V.
Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Voltage Applied to Outputs in High Z state DC Input Clamp Current DC Input Clamp Current Static Discharge Voltage (25 oC) Latch-up Current Symbol VDD VIN T Tstg Vhz Ilk Iok ESD Itrig 0 -65 -0.5 -20 -20 -2500 -400 Min Typ 3.3 TBD TBD TBD TBD TBD TBD TBD TBD +70 +150 TBD +20 +20 +2500 +400 Max Units V V oC oC V mA mA V mA
LAN-047, Rev. D
Conexant
PROPRIETARY INFORMATION
21
LANfinityTM RS7112
Multifunction Controller With HomePNA 1.0 Physical Layer
Table 7. AC Electrical Characteristics
TA = 0oC to +70oC, VDD = +3.3V 5%, VSS = 0V.
Parameter Frequency (PCI_CLK) Frequency (8023_MII_TX_CLK) 100 Mbps Frequency (8023_MII_RX_CLK) 100 Mbps Frequency (8023_MII_TX_CLK) 10 Mbps Frequency (8023_MII_RX_CLK) 10 Mbps Frequency (8023_MII_MDC) Symbol Fpck Fxtal TBD TBD TBD TBD Min 25 25 25 2.5 2.5 0 Typ 33 25 25 2.5 2.5 2.5 Max 33 25 25 2.5 2.5 2.5 Units MHz MHz MHz MHz MHz MHz
Note: Setup, Hold and Delays are with respect to the rising edge of the respective clock unless specified. PCI Bus signals conform to the PCI Bus Timing Specification. Table 8.
Mode Typical Current (mA) TBD TBD TBD
Current and Power Characteristics
Maximum Current (mA) TBD TBD TBD Typical Power (W) TBD TBD TBD Maximum Power (W) TBD TBD TBD Notes
Active Idle Power down
13 mm BGA - TBD
Table 9. Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Voltage Applied to Outputs in High Z state DC Input Clamp Current DC Input Clamp Current Static Discharge Voltage (25 oC) Latch-up Current Symbol VDD VIN T Tstg Vhz Ilk Iok ESD Itrig Min Typ Max Units V V oC oC V mA mA V mA
22
Conexant
PROPRIETARY INFORMATION
LAN-047, Rev. D
Multifunction Controller With HomePNA 1.0 Physical Layer
Table 10. DC Electrical Characteristics o o TA = 0 C to +70 C, VDD = +3.3V 5%, VSS = 0V.
Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Voltage Applied to Outputs in High Z state DC Input Clamp Current DC Input Clamp Current Static Discharge Voltage (25 oC) Latch-up Current Symbol VDD VIN T Tstg Vhz Ilk Iok ESD Itrig Min Typ Max
LANfinityTM RS7112
Units V V oC oC V mA mA V mA
Table 11. AC Electrical Characteristics TA = 0oC to +70oC, VDD = +3.3V 5%, VSS = 0V.
Parameter Frequency (PCI_CLK) Frequency (8023_MII_TX_CLK) 100 Mbps Frequency (8023_MII_RX_CLK) 100 Mbps Frequency (8023_MII_TX_CLK) 10 Mbps Frequency (8023_MII_RX_CLK) 10 Mbps Frequency (8023_MII_MDC) Symbol Fpck Fxtal Min Typ Max Units MHz MHz MHz MHz MHz MHz
Note: Setup, Hold and Delays are with respect to the rising edge of the respective clock unless specified. PCI Bus signals conform to the PCI Bus Timing Specification. Table 12.
Mode Typical Current (mA)
Current and Power Characteristics
Maximum Current (mA) Typical Power (W) Maximum Power (W) Notes
Active Idle Power down
LAN-047, Rev. D
Conexant
PROPRIETARY INFORMATION
23
LANfinityTM RS7112
Multifunction Controller With HomePNA 1.0 Physical Layer
Package Dimensions
Figure 6. 176-Pin TQFP Package Dimensions
24
Conexant
PROPRIETARY INFORMATION
LAN-047, Rev. D
Multifunction Controller With HomePNA 1.0 Physical Layer
LANfinityTM RS7112
0.12 Z X Z 0.10 4X
0.36 +/- 0.05 0.10 Z
A1 BALL PAD CORNER
13.00 1.40 +/- 0.10
Y
5
0.46 TYP 0.15 M Z X Y 0.08 M Z
13.00
6
SEATING PLANE
0.70 +/- 0.05
TOP VIEW
A1 BALL PAD CORNER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SIDE VIEW
0.80
A B C D E F G H J K
0.90 REF
L M N P R
0.90 REF
0.80
BOTTOM VIEW
(176 SOLDER BALLS)
All dimensions in millimeters
Figure 7. 13 mm BGA Package Dimensions
LAN-047, Rev. D
Conexant
PROPRIETARY INFORMATION
25
Further Information: literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com World Headquarters Conexant Systems, Inc. 4311 Jamboree Road, P.O. Box C Newport Beach, CA 92658-8902 Phone: (949) 483-4600 Fax: (949) 483-6375 U.S. Florida/South America Phone: (727) 799-8406 Fax: (727) 799-8306 U.S. Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 U.S. Mid-Atlantic Phone: (215) 244-6784 Fax: (215) 244-9292 U.S. North Central Phone: (630) 773-3454 Fax: (630) 773-3907 U.S. Northeast Phone: (978) 692-7660 Fax: (978) 692-8185 U.S. Northwest/Pacific West Phone: (408) 249-9696 Fax: (408) 249-7113 U.S. South Central Phone: (972) 733-0723 Fax: (972) 407-0639 U.S. Southeast Phone: (919) 858-9110 Fax: (919) 858-8669 U.S. Southwest Phone: (949) 483-9119 Fax: (949) 483-9090 APAC Headquarters Conexant Systems Singapore, Pte. Ltd. 1 Kim Seng Promenade Great World City #09-01 East Tower Singapore 237994 Phone: (65) 737 7355 Fax: (65) 737 9077 Australia Phone: (61 2) 9869 4088 Fax: (61 2) 9869 4077 China Phone: (86 2) 6361 2515 Fax: (86 2) 6361 2516
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